The present invention relates to a method for driving a semiconductor memory including a ferroelectric capacitor.
A known semiconductor memory including a ferroelectric capacitor is composed of, as shown in FIG. 6, a field effect transistor (hereinafter referred to as the FET) 1 having a drain region 1a, a source region 1b and a gate electrode 1c, and a ferroelectric capacitor 2 having an upper electrode 2a, a lower electrode 2b and a ferroelectric film 2c. This semiconductor memory employs the non-destructive read-out system in which the lower electrode 2b of the ferroelectric capacitor 2 is connected to the gate electrode 1c of the FET 1, so as to use the ferroelectric capacitor 2 for controlling the gate potential of the FET 1. In FIG. 6, a reference numeral 3 denotes a substrate.
In writing a data in this semiconductor memory, a writing voltage is applied between the upper electrode 2a of the ferroelectric capacitor 2, which works as a control electrode, and the substrate 3.
For example, when a data is written by applying a voltage (control voltage) positive with respect to the substrate 3 to the upper electrode 2a, downward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, positive charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has positive potential.
When the potential of the gate electrode 1c exceeds the threshold voltage of the FET 1, the FET 1 is in an on-state. Therefore, when a potential difference is induced between the drain region 1a and the source region 1b, a current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory is defined, for example, as xe2x80x9c1xe2x80x9d.
On the other hand, when a voltage negative with respect to the substrate 3 is applied to the upper electrode 2a of the ferroelectric capacitor 2, upward polarization is caused in the ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter, even when the upper electrode 2a is grounded, negative charge remains in the gate electrode 1c of the FET 1, and hence, the gate electrode 1c has negative potential. In this case, the potential of the gate electrode 1c is always lower than the threshold voltage of the FET 1, the FET 1 is in an off-state. Therefore, even when a potential difference is induced between the drain region 1a and the source region 1b, no current flows between the drain region 1a and the source region 1b. Such a logical state of the ferroelectric memory is defined, for example, as xe2x80x9c0xe2x80x9d.
Even when the power supply to the ferroelectric capacitor 2 is shut off, namely, even when the voltage application to the upper electrode 2a of the ferroelectric capacitor 2 is stopped, the aforementioned logical states are retained, and thus, a nonvolatile memory is realized. Specifically, when power is supplied again to apply a voltage between the drain region 1a and the source region 1c after shutting off the power supply for a given period of time, a current flows between the drain region 1a and the source region 1b if the logical state is xe2x80x9c1xe2x80x9d, so that the data xe2x80x9c1xe2x80x9d can be read, and no current flows between the drain region 1a and the source region 1b if the logical state is xe2x80x9c0xe2x80x9d, so that the data xe2x80x9c0xe2x80x9d can be read.
In order to correctly retain a data while the power is being shut off (which characteristic for retaining a data is designated as retention), it is necessary to always keep the potential of the gate electrode 1c of the FET 1 to be higher than the threshold voltage of the FET 1 when the data is xe2x80x9c1xe2x80x9d and to always keep the potential of the gate electrode 1c of the FET 1 at a negative voltage when the data is xe2x80x9c0xe2x80x9d.
While the power is being shut off, the upper electrode 2a of the ferroelectric capacitor 2 and the substrate 3 have ground potential, and hence, the potential of the gate electrode 1c is isolated. Therefore, ideally, as shown in FIG. 7, a first intersection c between a hysteresis loop 4 obtained in writing a data in the ferroelectric capacitor 2 and a gate capacitance load line 7 of the FET 1 obtained when a bias voltage is 0 V corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c1xe2x80x9d, and a second intersection d between the hysteresis loop 4 and the gate capacitance load line 7 corresponds to the potential of the gate electrode 1c obtained in storing a data xe2x80x9c0xe2x80x9d. In FIG. 7, the ordinate indicates charge Q appearing in the upper electrode 2a (or the gate electrode 1c) and the abscissa indicates voltage V.
Actually, however, the ferroelectric capacitor 2 is not an ideal insulator but has a resistance component, and hence, the potential of the gate electrode 1c drops through the resistance component. This potential drop is exponential and has a time constant obtained by multiplying parallel combined capacitance of the gate capacitance of the FET 1 and the capacitance of the ferroelectric capacitor 2 by the resistance component of the ferroelectric capacitor 2. The time constant is approximately 104 seconds at most. Accordingly, the potential of the gate electrode 1c is halved within several hours.
Since the potential of the gate electrode 1c is approximately 1 V at the first intersection c as shown in FIG. 7, when the potential is halved, the potential of the gate electrode 1c becomes approximately 0.5 V, which is lower than the threshold voltage of the FET 1 (generally of approximately 0.7 V). As a result, the FET 1 that should be in an on-state is turned off in a short period of time.
In this manner, although the ferroelectric memory using the ferroelectric capacitor for controlling the gate potential of the FET has an advantage that a rewrite operation is not necessary after a data read operation, it has the following problem: The gate electrode 1a of the FET 1 obtains potential after writing a data, and the ability for keeping the gate potential determines the retention characteristic. Since the time constant until discharge of the ferroelectric capacitor 2 is short due to the resistance component of the ferroelectric capacitor 2, the data retaining ability is short, namely, the retention characteristic is not good.
In consideration of the aforementioned conventional problem, an object of the invention is improving the retention characteristic of a semiconductor memory including a ferroelectric capacitor for storing a multi-valued data in accordance with displacement of polarization of a ferroelectric film thereof.
In order to achieve the object, the first method of this invention for driving a semiconductor memory including a ferroelectric capacitor for storing a multi-valued data in accordance with displacement of polarization of a ferroelectric film thereof and a reading field effect transistor that is formed on a substrate and has a gate electrode connected to a first electrode corresponding to one of an upper electrode and a lower electrode of the ferroelectric capacitor for detecting the displacement of the polarization of the ferroelectric film, comprises a first step of writing a multi-valued data in the ferroelectric capacitor by applying a relatively high first writing voltage or a relatively low second writing voltage between the first electrode and a second electrode corresponding to the other of the upper electrode and the lower electrode of the ferroelectric capacitor; a second step of removing a potential difference induced between the first electrode and the second electrode; and a third step of reading the multi-valued data by detecting the displacement of the polarization of the ferroelectric film by applying a reading voltage between the second electrode and the substrate, and the reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, a first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than a second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage.
In the first method for driving a semiconductor memory of this invention, after writing a multi-valued data in the ferroelectric capacitor, the potential difference induced between the first electrode and the second electrode of the ferroelectric capacitor is removed. Therefore, lowering of the potential of the gate electrode through a resistance component of the ferroelectric film due to the potential difference induced in the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic while the power is being shut off.
In this case, the potential difference induced between the first electrode and the second electrode of the ferroelectric capacitor is removed. However, since the reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, the first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than the second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage, the data stored in the ferroelectric capacitor can be read without fail.
In the first method for driving a semiconductor memory, the semiconductor memory preferably has a switch for equalizing potentials of the first electrode and the second electrode of the ferroelectric capacitor, and the second step preferably includes a sub-step of removing the potential difference by equalizing the potentials of the first electrode and the second electrode with the switch.
In this manner, the potential difference induced between the first electrode and the second electrode of the ferroelectric capacitor can be easily and definitely removed.
In the first method for driving a semiconductor memory, the third step preferably includes a sub-step of detecting the displacement of the polarization of the ferroelectric film by detecting whether a potential difference induced between the gate electrode and the substrate owing to division of the reading voltage in accordance with a ratio between capacitance of the ferroelectric capacitor and gate capacitance of the reading field effect transistor is relatively high or relatively low.
In this manner, the potential difference induced between the gate electrode and the substrate can be set to satisfy the aforementioned relationship, namely, the relationship in which the first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the relatively high first writing voltage is smaller than the potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the relatively low second writing voltage.
The second method of this invention for driving a semiconductor memory including a plurality of successively connected ferroelectric capacitors each for storing a multi-valued data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading field effect transistor that is formed on a substrate and has a gate electrode connected to one end of the plurality of successively connected ferroelectric capacitors for detecting the displacement of the polarization of the ferroelectric film of each of the successively connected ferroelectric capacitors, comprises a first step of writing a multi-valued data in one ferroelectric capacitor selected from the plurality of ferroelectric capacitors by applying a relatively high first writing voltage or a relatively low second writing voltage between an upper electrode and a lower electrode of the selected ferroelectric capacitor; a second step of removing a potential difference induced between the upper electrode and the lower electrode of the selected ferroelectric capacitor; and a third step of reading the multi-valued data by detecting the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor by applying a reading voltage between another end of the plurality of successively connected ferroelectric capacitors and the substrate, and the reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, a first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than a second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage.
In the second method for driving a semiconductor memory of this invention, after writing a multi-valued data in the ferroelectric capacitor, the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor is removed. Therefore, the lowering of the potential of the gate electrode through the resistance component of the ferroelectric film due to the potential difference induced in the ferroelectric capacitor can be avoided, resulting in improving the retention characteristic while the power is being shut off.
In this case, the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor is removed. However, since the reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, the first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than the second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage, the data stored in the ferroelectric capacitor can be read without fail.
In the second method for driving a semiconductor memory, the semiconductor memory preferably has a plurality of switches each for equalizing potentials of an upper electrode and a lower electrode of each of the plurality of ferroelectric capacitors, and the second step preferably includes a sub-step of removing the potential difference by equalizing the potentials of the upper electrode and the lower electrode of the selected ferroelectric capacitor with the switch.
In this manner, the potential difference induced between the upper electrode and the lower electrode of the ferroelectric capacitor can be easily and definitely removed.
In the second method for driving a semiconductor memory, the third step preferably includes a sub-step of detecting the displacement of the polarization of the ferroelectric film of the selected ferroelectric capacitor by detecting whether a potential difference induced between the gate electrode and the substrate owing to division of the reading voltage in accordance with a ratio between capacitance of the selected ferroelectric capacitor and gate capacitance of the reading field effect transistor is relatively high or relatively low.
In this manner, the potential difference induced between the gate electrode and the substrate can be set to satisfy the aforementioned relationship, namely, the relationship in which the first potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the relatively high first writing voltage is smaller than the potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the relatively low second writing voltage.